Raw Architecture Small Replicated Tiles

86 Computer A s our industry develops the technology that will permit a billion transistors on a chip, computer architects must face three converging forces: the need to keep internal chip wires short so that clock speed scales with feature size; the economic constraints of quickly verifying new designs; and changing application workloads that emphasize stream-based multimedia computations. One approach is to rely on a simple, highly parallel VLSI architecture that fully exposes the hardware architecture's low-level details to the compiler. This allows the compiler—or, more generally, the soft-ware—to determine and implement the best resource allocation for each application. We call systems based on this approach Raw architectures because they implement only a minimal set of mechanisms in hardware. Raw machines require only short wires, are much simpler to design than today's superscalars, and support efficient pipelined parallelism for multimedia applications. Our general philosophy is to build an architecture based on replicating a simple tile, each with its own instruction stream. As Figure 1 shows, a Raw microprocessor is a set of interconnected tiles, each of which contains instruction and data memories, an arithmetic logic unit, registers, configurable logic, and a pro-grammable switch that supports both dynamic and compiler-orchestrated static routing. The tiles are connected with programmable, tightly integrated interconnects. The tightly integrated, synchronous network interface of a Raw architecture allows for intertile communication with short latencies similar to those of register accesses. Static scheduling guarantees that operands are available when needed, eliminating the need for explicit synchronization. In addition, each tile supports multigranular (bit-, byte-and word-level) operations and programmers can use the configurable logic in each tile to construct operations uniquely suited to a particular application. Together, these features will enable high switching speeds and dramatically simplify hardware design and verification tasks. As Figure 1 shows, a Raw machine is made up of a set of interconnected tiles. Each tile contains a simple, RISC-like pipeline and is interconnected with other tiles over a pipelined, point-to-point network. Having many distributed registers eliminates the small-register name-space problem, allowing a greater degree of instruction-level parallelism (ILP). Static RAM (SRAM) distributed across the tiles eliminates the memory bandwidth bottleneck and provides significantly shorter latency to each memory module. The distributed architecture also allows multiple high-bandwidth paths to external Rambus-like DRAM—as many as packaging technology will permit. A typical Raw system might include a Raw microprocessor coupled with off-chip memory and stream-IO devices. The …